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W24L010A 128K x 8 HIGH SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L010A is a high speed, low power CMOS static RAM organized as 131072 x 8 bits that operates on a single 3.3-volt power supply. This device is manufactured using Winbond's high performance CMOS technology.
FEATURES
* *
High speed access time:10/12/15 nS (max.) Low power consumption: - Active: 300 mW (typ.)
* * *
All inputs and outputs directly TTL/LVTTL compatible Three-state outputs Available packages: 32-pin 300 mil SOJ, skinny DIP and TSOP
* *
Single +3.3V power supply Fully static operation
PIN CONFIGURATIIONS
BLOCK DIAGRAM
V DD
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 1 I/O 2 I/O 3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4
VSS A0 . . A16
DECODER
CORE C O RE ARRAY
CS2 CS1 OE WE CONTROL DATA I/O I/O1 . . I/O8
PIN DESCRIPTION
SYMBOL A0-A16 I/O1-I/O8 CS1, CS2 WE OE VDD VSS NC DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection
A11 A9 A8 A13 WE CS2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-pin TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS DQ3 DQ2 DQ1 A0 A1 A2 A3
-1-
Publication Release Date: September 1999 Revision A2
W24L010A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature RATING -0.5 to +4.6 -0.5 to VDD +0.5 1.0 -65 to +150 0 to +70 UNIT V V W C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
TRUTH TABLE
CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L MODE Not Selected Not Selected Output Disable Read Write I/O1-I/O8 High Z High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 ISB, ISB1 IDD IDD IDD
OPERATING CHARACTERISTICS
(VDD = 3.3V 5%, VSS = 0V, TA = 0 to 70 C)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current
SYM. VIL VIH ILI ILO VOL VOH IDD
TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL IOL = +8.0 mA IOH = -4.0 mA 10 CS1 = VIL, CS2 = VIH I/O = 0 mA Cycle = MIN Duty = 100% CS1 VDD -0.2V or CS2 0.2V 12 15
MIN. -0.5 +2.0 -10 -10 2.4 -
TYP. -
MAX. +0.8 DD +0.5 V +10 +10 0.4 130 120 100 15 5
UNIT V V A A V V mA mA mA mA mA
Standby Power Supply Current
ISB ISB1
CS1 = VIH, or CS2 = VIL
Note: Typical characteristics are at VDD = 3.3V, TA = 25 C.
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W24L010A
CAPACITANCE
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 8 10
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 3 nS 1.5V CL = 30 pF, IOH/IOL = -4 mA/8 mA CONDITIONS
AC TEST LOADS AND WAVEFORM
R1 320 ohm R1 320 ohm 3.3V OUTPUT 30 pF Including Jig and Scope R2 350 ohm 3.3V OUTPUT 5 pF Including Jig and Scope R2 350 ohm
(For T CLZ1, TCLZ2, TOLZ, TCHZ1, TCHZ2, TOHZ, TWHZ, TOW )
3.0V
90% 10% 3 nS 10%
90%
0V
3 nS
-3-
Publication Release Date: September 1999 Revision A2
W24L010A
AC CHARACTERISTICS
(VDD = 3.3V 5%, VSS = 0V, TA = 0 to 70 C)
Read Cycle
PARAMETER SYM. W24L010A10 MIN. Read Cycle Time Address Access Time Chip Select Access Time CS1 CS2 Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z CS1 CS2 CS1 CS2 TRC TAA TACS1 TACS2 TAOE TCLZ1* TCLZ2* TOLZ* TCHZ1* TCHZ2* TOHZ* TOH 10 3 3 0 3 MAX. 10 10 10 5 5 5 5 W24L010A12 MIN. 12 3 3 0 3 MAX. 12 12 12 6 6 6 6 W24L010A15 MIN. 15 3 3 0 3 MAX. 15 15 15 7 7 7 7 nS nS nS nS nS nS nS nS nS nS nS nS UNIT
Output Disable to Output in High Z Output Hold from Address Change
* These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER SYM. W24L010A10 MIN. Write Cycle Time Chip Selection to End of CS1 TWC TCW1 TCW2 TAW TAS TWP TWR1 TWR2 TDW TDH TWHZ* TOHZ* TOW 10 9 9 9 0 9 0 0 5 0 0 MAX. 5 5 W24L010A12 MIN. 12 10 10 10 0 10 0 0 7 0 0 MAX. 6 6 W24L010A15 MIN. 15 13 13 13 0 10 0 0 9 0 0 MAX. 8 8 nS nS nS nS nS nS nS nS nS nS nS nS nS UNIT
Write CS2 Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery CS1, WE
Time CS2 Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write
* These parameters are sampled but not 100% tested.
-4-
W24L010A
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
TRC Address TOH DOUT TAA TOH
Read Cycle 2
(Chip Select Controlled)
CS1 TACS1 CS2 TACS2 TCHZ2 TCHZ1
TCLZ1 DOUT TCLZ2
Read Cycle 3
(Output Enable Controlled)
TRC Address TAA OE TAOE CS1 TOLZ TACS1 TCLZ1 CS2 TACS2 TCLZ2 DOUT TCHZ2 TOHZ TCHZ1 TOH
-5-
Publication Release Date: September 1999 Revision A2
W24L010A
Timing Waveforms, continued
Write Cycle 1
(OE Clock)
T WC Address TWR1 OE TCW1 CS1
CS2 TAW WE TAS TOHZ D OUT (1, 4)
TCW2 TWR2 TWP
TDW D IN
TDH
Write Cycle 2 (OE = VIL Fixed)
TWC Address T CW1 CS1 TWR1
CS2 TAW WE TAS
TCW2 TWR2 T WP TWHZ (1, 4) TOH TOW TDH (2) (3)
D OUT TDW D IN
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. Dout provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
-6-
W24L010A
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 10 12 15 10 12 15 10 12 15 OPERATING CURRENT MAX. (mA) 130 120 100 130 120 100 130 120 100 STANDBY CURRENT MAX. (mA) 5 5 5 5 5 5 5 5 5 PACKAGE
W24L010AK-10 W24L010AK-12 W24L010AK-15 W24L010AJ-10 W24L010AJ-12 W24L010AJ-15 W24L010AT-10 W24L010AT-12 W24L010AT-15
300 mil skinny DIP 300 mil skinny DIP 300 mil skinny DIP 300 mil SOJ 300 mil SOJ 300 mil SOJ Type one TSOP Type one TSOP Type one TSOP
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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Publication Release Date: September 1999 Revision A2
W24L010A
PACKAGE DIMENSIONS
32-pin P-DIP Skinny (300 mil)
Symbol
Dimension in Inches Dimension in mm
Min. Nom. Max.
0.200 0.015 0.145 0.016 0.058 0.008 0.150 0.018 0.060 0.010 1.60 0.295 0.286 0.090 0.120 0 0.430 0.450 0.315 0.290 0.100 0.130 0.155 0.022 0.064 0.014 1.62 0.335 0.294 0.110 0.140 15 0.470 0.065
Min. Nom. Max.
5.08 0.38 3.68 0.41 1.47 0.20 3.81 0.46 1.52 0.25 40.64 7.49 7.26 2.29 3.05 0 10.92 11.43 8.00 7.36 2.54 3.30 3.94 0.56 1.63 0.36 41.15 8.50 7.46 2.79 3.56 15 11.94 1.65
D
32 17
E1
1
16
A A1 A2 B B1 c D E E1 e1 L
a
eA S Notes:
S E
Base Plane
A A2 L A1
c
Mounting Plane
B1 B e1 a eA
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
32-pin SOJ
Dimension in Inches 32 17 Dimension in mm
Symbol A A1 A2
E He
Min.
__ 0.020 0.095 0.026 0.016 0.008 0.815 0.295 0.044 0.247 0.325 0.080 __ __ 0
Nom. Max.
__ __ 0.100 0.028 0.018 0.010 0.825 0.300 0.050 0.267 0.335 __ __ __ __ 0.140 __ 0.105 0.032 0.022 0.014 0.835 0.305 0.056 0.287 0.345 __ 0.045 0.004 10
Min.
__ 0.508 2.413 0.660 0.406 0.203 20.701 7.493 1.118 6.274 8.255 2.032 __ __ 0
Nom. Max.
__ __ 2.540 0.711 0.457 0.254 20.955 7.620 1.270 6.782 8.509 __ __ __ __ 3.556 __ 2.667 0.813 0.559 0.356 21.209 7.747 1.422 7.290 8.763 __ 1.143 0.102 10
B b c D E e e1
1
16
He L S Y
D
A2
A L
c
e1
S B b
e
A1
Y
Seating Plane
-8-
W24L010A
Package Dimensions, continued
32-pin TSOP
HD
Symbol Dimension in Inches Min. Nom. Max.
0.047 0.002 0.037 0.007 0.005 0.720 0.311 0.780
Dimension in mm Min. Nom. Max.
1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20
D c
A A1 A2
__
__ __
0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031 0.006 0.041 0.009 0.007
__
0.05 0.95 0.17 0.12
__ __
1.00 0.20 0.15
M
e E
b c D E HD e L L1
A A2
0.10(0.004)
0.728 18.30 18.40 0.319 0.795 7.90 19.80 8.00 20.00 0.50 0.50 0.80
b
__
0.016
__
0.024
__
0.40
__
0.60
__
0.000 1
__
0.004 5
__
0.00 1
__
0.10 5
Y Y
__
3
__
3
L L1
A1
Note:
Controlling dimension: Millimeter
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
-9-
Publication Release Date: September 1999 Revision A2

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